Research Papers Compiler Design

Research Papers Compiler Design-61
The performance of the translated code is better than the widely-used commercial Rosetta translator (shipped with Apple's OS X) at that time.

The performance of the translated code is better than the widely-used commercial Rosetta translator (shipped with Apple's OS X) at that time.The paper provides techniques to dynamically map the state of one machine to the state of another machine in tandem with synthesis-based code generation, for better overall quality of the generated code.

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The ideas are evaluated over a wide range of workloads for several metrics.

The Unicorn Runtime: Efficient distributed shared memory programming for hybrid CPU-GPU clusters How can a programmer harness the combined computing power of CPUs and GPUs in a computing cluster without dealing with all the nitty gritties of the underlying system and its optimizations?

Our current research is targetted towards generalizing and scaling the ideas presented in this paper.

CAR: Clock with Adaptive Replacement This paper extends the well-known CLOCK algorithm for cache replacement (used in most operating systems) with ideas presented in previous work on Adaptive Replacement Cache (ARC).

Here are the courses I am teaching in the current semester. We are working on an optimizing C compiler based on program synthesis and superoptimization techniques.

The primary ideas are: access-coverage based huge-page promotion, asynchronous page pre-zeroing, exploring the notion of fairness in dealing with huge-page allocations, and the effect of using hardware performance counters to estimate the benefits of huge-page allocations.The International Conference on Compiler Construction (CC) is interested in work on processing programs in the most general sense: analyzing, transforming or executing input that describes how a system operates, including traditional compiler construction as a special case.Original contributions are solicited on the topics of interest which include, but are not limited to: CC 2017 is the 26th edition of the conference.The capability of turning DBT on and off during system execution is quite cool, and did not exist in any previous DBT system.The orchestration of translated instructions in the processor's instruction cache to the performance of the system (i.e., the translated system can be faster than the native system) is quite interesting.Binary Translation Using Peephole Superoptimizers Can we automatically infer translations from one architecture to another using synthesis and superoptimization techniques?This paper demonstrates such capability for Power PC to x86 translation.Papers must be written in English and be submitted in pdf in ACM SIGPLAN proceedings format, using the default 9pt font size.The proceedings will be published in the ACM Digital Library and will be made available freely for the period around the conference.Additional material intended for reviewers but not for publication in the final version (listings, data, proofs) may be included in a clearly marked appendix.Submitted papers must be unpublished and not be submitted for publication elsewhere.


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